The present invention relates to computer communication channels. In particular, the present invention relates to the synchronous control of a serial interface and to the maintenance of high data transfer rates between parallel and serial communication channels.
Communication protocols provide standards by which commands and data may be passed between various components associated with a computer system. In addition to establishing the standards for physical connections between devices, protocols establish the commands that can be transmitted, and they established the packaging and flow of data passed over the bus used in connection with the protocol.
Communications channels can be categorized as belonging to either of two methods for transferring commands and data. In one arrangement, a parallel communication scheme or protocol is used. A parallel protocol utilizes multiple signal lines for providing signals related to control of the bus, and multiple signal lines for transferring data between a bus controller and devices interconnected to the bus. Contrasted with parallel communication channels are serial channels. According to a serial communication scheme or protocol, device control signals, commands and data are transmitted in series along a single signal line.
At the interface between communication channels or busses, adapters may be used to translate from the protocol used by the first bus to the protocol used by the second bus. In order to accommodate differences in the amount of data provided to the adapter by one of the channels and the amount of data that can be received by the other of the channels, adapters commonly incorporate first-in first-out (FIFO) buffers at the interface between the first communication channel and the adapter, and at the interface between the second communication channel and the adapter. That is, the adapter provides memory in which data may be stored temporarily to accommodate different data transfer rates. The use of a FIFO buffer at the interface between the adapter and each of the channels also allows variations in the amount of time required by the adapter to, for example, perform error checking functions, to be accommodated. However, the use of buffers at the interface between both the first communication channel and the adapter and the second communication channel and the adapter introduces delays in the transfer of data between the first and second channels. In addition, the management of multiple buffers complicates the operation of the adapter, and adds to the processing overhead of the adapter.
Therefore, it would be desirable to provide for an adapter capable of interfacing a parallel communication channel to a serial communication channel that did not require the use of multiple data buffers. Furthermore, it would be advantageous to interface a parallel communication channel to a serial communication channel such that the conversion between the serial and the parallel protocols was performed without introducing variable delays. In addition, it would be advantageous to provide an adapter for interfacing parallel communication channel to a serial communication channel that was reliable in operation and inexpensive to implement.
In accordance with the present invention, a method and an apparatus for interfacing a serial communication channel to a parallel communication channel are provided. The present invention generally provides an adapter for providing such an interface that does not require the use of a first-in first-out (FIFO) buffer in connection with the link layer that is in communication through the physical layer with a device utilizing a serial communications protocol. In particular, the need for such a buffer is removed by synchronously controlling the operation of the serial interface. Accordingly, the present invention provides an interface that is capable of decreasing delays in transferring data as compared to a conventional adapter. In addition, the processing overhead associated with control of a buffer associated with the link is eliminated by eliminating a FIFO buffer in the link or at the interface between the transport and the link. Furthermore, the need to provide space for a FIFO buffer between the link layer and the host interface is eliminated.
In accordance with an embodiment of the present invention, an adapter comprising a host interface, transport, link, and physical layers is provided. In connection with the host interface, a FIFO buffer is provided for synchronizing the transfer of data between a host bus and the adapter. The link layer is interconnected to a device utilizing a serial communication protocol through the physical layer. No FIFO buffer is provided in connection with the link layer. Accordingly, the operation of the transport, link, and physical layers are coordinated or synchronized. As a result, delays encountered in passing data between the parallel communication bus and the serial communication bus is limited. In particular, the time for a frame of data of a first length to pass between the FIFO associated with the transport and the device is predetermined. In accordance with an embodiment of the present invention, the transport layer controls the passage of data between the various layers of the adapter.
In accordance with another embodiment of the present invention, a method is provided for synchronous control of a serial interface. According to the method, a data frame of a first length is passed from the FIFO of the host interface to the device in a first number of clock cycles. Accordingly, the serial communications channel is capable of transferring a data frame of a first length across the serial channel in a first number of clock cycles. A parallel data channel within the adapter, having an operating frequency different from the operating frequency of the serial data channel and interconnecting the link to the host interface, is capable of transferring a data frame of the first length across the parallel data channel in a second number of clock cycles. According to the method, the ratio of the number of clock cycles required for the serial data channel to pass a frame of a given length to the number of clock cycles required for the internal parallel channel to pass the same frame is fixed. Because the ratio of the number of clock cycles required for the adapter to transfer a frame of data between the interface with the serial communication channel and the FIFO of the interface with the parallel communication channel is fixed, there is no need to provide a FIFO buffer in connection with the transport layer. Accordingly, delays in transferring data that might occur as a result of that data being held in a buffer in the transport layer are removed. In addition, overhead associated with the control of a FIFO at the serial communication channel side of the adapter is avoided.
Additional advantages of the present invention will become readily apparent from the following discussion, particularly when taken together with the accompanying drawings.